1. Field of the Invention
The present invention relates to electrically erasable programmable read only memory (EEPROM) devices and, in particular, to an EEPROM cell structure that employs a tunnel window region fabricated using self-alignment techniques.
2. Discussion of the Prior Art
Floating-gate electron tunneling MOS (FETMOS) structures have been successfully used to accomplish reliable charge transfers to the floating gate in EEPROM cell structures. See C. Kuo, et al., IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 5, October 1982, pp. 821-827. The FETMOS device relies on Fowler-Nordheim tunneling of electrons between the floating gate and the substrate to accumulate charge on the floating gate for program or erase operations. FETMOS devices use an isolated polysilicon node as the floating gate and silicon dioxide (SiO.sub.2) to insulate the floating gate.
A conventional FETMOS cell is depicted in FIGS. 1-3. The oxide region underlying the floating gate consists of a uniform sheet of thin tunnel oxide, typically less than about 200 .ANG. thick. The control gate is separated from the floating gate by a thicker insulator, typically oxide/nitride/oxide (ONO).
To erase a programmed EEPROM cell, a high voltage is applied to the control gate, while both the drain and the source of the FETMOS are grounded. The amount of voltage coupled to the floating gate through capacitive coupling is sufficient to create an electric field in the thin tunnel oxide for tunneling of electrons from the substrate to the floating gate. The resulting accumulation of negative charge on the floating gate shifts the FETMOS threshold voltage to a more positive value.
Conversely, to program the cell, a high voltage is applied to the drain, while the control gate is grounded and the source is either biased at +5V or allowed to float. The electric field created in the thin tunnel oxide between the floating gate and the overlapped portion of the drain causes electrons to tunnel from the floating gate to the drain. This results in an accumulation of positive charge on the floating gate and a negative shift of the FETMOS threshold voltage.
In order to remove electrons from the floating gate, an edge of the N+ drain diffusion of the selected cell underlaps at least one edge of the cell's floating gate. This underlap creates problems. See T. Y. Chan, et al., IEDM 1987, CH2515-5/87/0000-0718, pp. 718-721. For example, the gate-to-drain overlap region creates a deep depletion region under the tunnel oxide that overlaps the drain. In the presence of the very high electric field which exists during programming operations, band-to-band tunneling increases the drain leakage current. Electron-hole pairs are generated by the tunneling of valence band electrons into the conduction band and collected by the drain and substrate. The holes that escape into the substrate via this mechanism represent an undesired leakage current. This leakage current increases over time each time the cell is subsequently programmed, because the leakage current leads to increased trap generation in the tunnel oxide. The creation of an electron trap in the tunnel oxide between the floating gate and the drain impedes the mechanism for charge transferral during erasing and programming operations. Therefore, the endurance characteristic of the cell is lessened. In other words, fewer re-program cycles may be executed before the cell fails to program correctly.
Another problem with the conventional FETMOS EEPROM cell is that the tunnel oxide extends all the way to the field oxide interface. Typically, the field oxide will at least partially cover the drain and/or source regions, tapering away into a "bird's beak" along its boundaries. It is well known that stress along the edge of the field oxide bird's beak region will degrade the quality of a thin oxide grown in this region. Any defect or discontinuity of the thin oxide region can lead to unintended connections which give rise to defective bits in the memory array. Thus, an increase in the incidence of defective bits and a decrease in the yield results from the extension of the tunnel oxide over the drain and to the interface with the field oxide.
The well-known FLOTOX (floating gate tunnel oxide) EEPROM cell overcomes the problems associated with the above-described FETMOS cell. See W. S. Johnson, et al., 1980 IEEE International Solid-State Circuits Conference, pp. 152-153. FIGS. 4 and 5 show a conventional FLOTOX cell. Most of the floating gate of the FLOTOX cell overlies a thicker gate oxide (typically 300 to 400 .ANG.). The FETMOS cell's problems with leakage current are avoided in the FLOTOX cell because the edges of the drain diffusion terminate under thicker gate oxide; thus, the field across the oxide during programming is lower, and there is less chance of generating leakage current due to band-to-band tunnelling. Since the termination of the drain diffusion region is far away from the tunnel oxide, the source of any leakage current is remote from the delicate tunnel oxide region, and degradation due to the generation of electron traps is minimized. Furthermore, because the tunnel window in the FLOTOX cell is small, and is surrounded on all sides within the same plane by thicker gate oxide, the tunnel oxide is kept away from the field oxide edge and the stress which accompanies the edge.
Although the FLOTOX cell remedies two key problems associated with the FETMOS cell, it presents additional problems. First, the FLOTOX cell introduces additional masking steps to the process sequence, thus increasing the cost of fabrication and increasing the sources for potential defects. Second, the formation of the tunnel oxide region and the buried N+ diffusion regions are not self-aligned steps. Thus, the height of the memory cell is increased. For instance, as shown in FIG. 4, in a typical FLOTOX cell layout, the overlap of the upper edge of the floating gate over the buried N+ drain region is 3.lambda., where .lambda. is the minimum design rule feature of the fabrication process.